This invention relates to a programmable device, and more particularly to, a programmable cell and a wiring network composing a programmable device, e.g., FPGA (field programmable gate array).
Programmable devices, typically FPGA, are LSIs that store configuration information to specify how to configure a hardware, and that create a desired hardware according to instructions from the configuration information. Recently, according as the scale of hardware capable of being created by the programmable device is enlarged due to advance in semiconductor fabrication technology, the switching from gate array LSI to programmable device is accelerated and is getting a lot of attention. In general, such a programmable device is needed to create a hardware with arbitrary functions, but it is difficult to create a large-scale circuit because the circuit scale of programmable cell to create an arbitrary logic is increased due to the general-purpose requirement. So, a cell and chip architecture capable of mounting a larger circuit is needed.
Also, depending on a circuit created, the wiring between logic gates is increased, and therefore the programmable cell is short of wiring resource. So, more wiring resource is required.
To comply with these requirements, for example, Japanese patent application No. 10-309285 (1998) discloses a technique that arbitrary logic, memory and wire connection are created by programmable cells, thus satisfying the requirements to hardware scale and wiring resource. In this technique, the memory and wire connection are provided as modes of programmable cell. Thus the memory, which yields an insufficiency if provided by a logic gate, can be created sufficiently. Also, by using the cell as the wiring resource when being short of wiring resource, a large-scale circuit can be created efficiently.
Also, Japanese patent application laid-open No. 7-273640 (1995) discloses a FPGA device where a programmable logic circuit, as shown in FIG. 1, includes a multiplexer 103 to switch between data stored in a memory cell 102 and external data signal as one input to a comparator 104. By arraying such programmable logic circuits and decoders (not shown) two-dimensionally, compact ROM, associative memory and multi-port register file are configured.
Japanese patent application laid-open No. 9-83347 (1997) discloses FPGA with multi-port RAM where first and second RAM cells 102, 108 are, as shown in FIG. 2, connected to corresponding first and second read/write ports 104, 110. The RAM cell functions independently as a single-port RAM when switched off by a switching device 114. However, the RAM cell shares data to function collectively as a double-port RAM when connected by the switching device 114.
Japanese patent application laid-open No. 9-186581 (1997) discloses a field programmable memory array where address decoder, hierarchical bit-line array, input/output device are, as shown in FIG. 3, programmable, and each part of array can be programmed into selection mode.
Japanese patent application laid-open No. 10-240678 discloses an extended input/output bus where as show in FIG. 4a FPGA 3 disposed between a master processor 1 and a slave processor 4 operates as a FIFO (first-in first-out memory) composed registers of arbitrary number by selecting configuration signal D. Multiple configuration signals D are read from configuration ROM 7, and a selector 6 selects one of them.
However, in prior arts, when it is not necessary to use the programmable cell as wiring resource or memory, the wiring-resource mode and the memory mode of programmable cell becomes unnecessary, and therefore an overhead of circuit and area provided in programmable cell is useless. Also, due to the addition of mode, the circuit and area of one programmable cell increases and the number of programmable cells mountable on the chip decreases. Therefore, the circuit scale created reduces. Furthermore, for example, when creating a FIFO circuit, a programmable cell that is unable to do the write and read of memory simultaneously requires a lot of programmable cells.
Here, the overhead due to addition of mode in programmable cell is explained.
FIG. 5 shows an example of configuration that a 4-input 1-output logic for arbitrary logic and a 16-bit RAM are created by mode switching. When this circuit operates as the 4-input 1-output circuit, storage information in storage element 801 is unnecessary to rewrite because it takes the content of a look-up table to enable an arbitrary logic. So, in operation, data are input to IN1 to IN4, and then information of a storage element 801 corresponding to an address input is read, thereby creating an arbitrary logic. On the other hand, when this circuit operates as the 16-bit RAM, in read operation, address data is input to IN1 to IN4, and then information of storage element 801 corresponding to the address data is read. This is the same operation as in case of 4-input 1-output circuit. However, when writing data, new paths are need and therefore write buffers 805 and its associated wiring become an overhead.
FIG. 6 shows an example of programmable cell that a 4-input 1-output logic for arbitrary logic, a 16-bit RAM, a crossbar switch of 4 in the vertical direction and 4 in the horizontal directions are created by mode switching. In this programmable cell, neighboring programmable cells in vertical and horizontal and the wiring networks are connected by input/output ports 901. Also, selectors are provided neighboring the programmable cell in the vertical and horizontal directions, and they control the connection between the input/output port and the memory means. In operation, when the programmable cell operates as the 4-input 1-output circuit or 16-bit RAM, data and address signal are input through the address input terminal, output through the data output terminal. Also, when the programmable cell operates as the crossbar switch, the neighboring programmable cells in vertical and horizontal, the wiring networks and the memory means are connected by the wiring of 4 each in vertical and horizontal directions, and the vertical wiring and horizontal wiring are connected together according to information of storage element. Therefore, the main overhead of the crossbar switch mode is brought by the vertical and horizontal wiring and the switch elements.
Accordingly, it is an object of the invention to provide a programmable device that the area efficiency in logic circuit is improved to offer a larger-scale circuit.
It is a further object of the invention to provide a programmable cell that offers multi-port memory.
According to the invention, a programmable device, comprises:
a programmable cell that operates as programmable logic or memory by internal storage means; and
a wiring network that is composed of a plurality of wiring lines and determines the line-connection state of a wiring group according to the storage means;
wherein the programmable cell is provided with n sets of input/output port groups, where n is an integer of 2 or more, and the wiring network is of m sets, where m is an integer of 2 or more.
According to another aspect of the invention, a programmable device, comprises:
a two-dimensional array of storage elements;
a decoder to select the storage element;
a buffer to input write signal; and
a selector to output selecting the output of the storage element;
wherein the decoder and the selector are configured into 2 or more groups, the control signal for the 2 or more groups is input to the decoder and the selector, and the storage element is configured into a group that the write signal is written and a group that signal written already is read out.
According to another aspect of the invention, a programmable device, comprises:
a two-dimensional array of programmable cells; and
two or more wiring network groups;
wherein each of the input/output port groups of programmable cell is connected to each of the wiring network groups, and signal with a same or different functions is input to each of the wiring groups.
According to another aspect of the invention, a programmable device, comprises:
a two-dimensional array of pairs of storage element and switch element; and
a selector to select one of the pairs;
wherein data signal, address signal and control signal are input to the selector, the pair is operated as either storage element or switch element according to the control signal, and output from the output port of the pair is output through the selector.